A serial peripheral interface (SPI), is a three wire or three line serial interface which uses a control unit to write data to an internal latch in a peripheral device. The three lines or wires are SYNCB, SDIN, and SCLK. SYNCB controls the time period when the controlling unit is writing to the peripheral device. When SYNCB is low, writing is taking place. When SYNCB is high, the peripheral device updates the internal latch to complete the write operation and ignores any other signals it receives. SDIN is a serial-data-in line which provides data that the controlling unit is writing to the peripheral device. SCLK carries the clock signal. It controls clocking in of the data that the controlling unit writes to the peripheral device during the period when the SYNCB signal is low. On each positive going SCLK edge, data on the SDIN line is sampled or brought into a shift register. Later, when the SYNCB line goes high, this data is moved into the internal latch. The peripheral device then processes the data which is present in the internal latch. The addition of a fourth wire or line serial data out (SDO) enables daisy chaining. The SDO line provides a copy of the SDIN data delayed by a number of clock signals. For example, where the data being read in is in 4-bit sets in the shift register and the internal latch, the copy of the data on the SDO line is a copy of the data on the SDIN line delayed by four clock cycles. In this way, it is possible to daisy chain several peripheral devices by connecting the SDO of one to the SDIN of the next. All of the peripheral devices, therefore share common SCLK and SYNCB signals. Then, if SYNCB is held low for a multiple of the data width, e.g., in this case four, then all but the last four bits of SDIN data pass through the first peripheral device from its SDIN input to its SDO output and to a second device or third or fourth. When the SYNCB line returns high, the internal four-bit latch in each of the peripheral devices can be simultaneously updated. In effect, the shift registers in each peripheral device are interconnected to create an effectively longer shift register distributed among several peripheral devices. In some implementations, it is desirable to update the internal latch from the shift register sometime after the write operation into the shift register has been completed. For this purpose, a fifth line called LOADB is used. Under these circumstances the internal latch is not updated at the end of a write when SYNCB returns high but rather is updated when the LOADB line is low. In some cases, it is desirable to know what value is in the internal latch, that is the value that is currently being processed by the peripheral device. Reading back this value in the latch is called read-back and requires yet another, sixth, line, the READB line. When the READB line goes low, and provided that the SYNCB line is high, the set of bits in the internal latch is read out to the shift register where it is provided on the SDO line.
While the present six wire or line system provides full read-write capability, it does have a shortcoming in that the transfer of the data bits from the internal latch to the shift register does not occur immediately when the READB line goes low but instead only upon the first rising edge of the CLK signal after the READB line goes low. This introduces a one clock cycle shift in the output on SDO with respect to the input on SDIN and so precludes daisy chaining. See U.S. Pat. Nos. 5,303,227; 5,128,666; 5,361,260; and Analog Devices, Inc. “AD5531 Datasheet” Rev O, 2002, http://products.analog.com/products/info.asp?product=AD5531